Chip Physical Architect

Southampton, United Kingdom


Experience Required:

5-10 years

Vacancy Type:

Full-Time Regular


Travel Percentage:

25


The Chip Physical Architect is responsible for understanding Design requirements and translating them into optimum IC implementations. In collaboration with IC Design Architects and System Architects, the key task is to achieve the best IC physical architecture. An environment to achieve these results is one of the aims of the SoC Design Environment (SoCDE).
The Chip Physical Architect is responsible for providing technical leadership and spearheading the Physical Design Flow implementation team. S/He will also be acting as technical interface representing the interests of Physical Design (in-house or third party) in the early phases of Design projects for lead customers.
The IC Physical Architect will be able to provide consultancy at various forums, e.g. World Wide Technical Conference (WWTC). The Chip Physical Architect will also be responsible for technical mentoring, support and technical direction for the group.
The Chip Physical Architect will evaluate new tools and methodologies to ensure that SoCDE is a “Best in Class” Design Environment. The Chip Physical Architect will actively keep abreast of industry trends and take a role in influencing future tools and methodologies provided by our major Vendors (Cadence, Mentor and Synopsys).






Essential/Job Requirements:


· Broad experience in all aspects of Physical Design, including electrical verification, signal integrity and physical verification.
· Have a good working knowledge of design-for-manufacture, EMC, ESD and Latch-up.
· Expert in floor-planning, partitioning and power-planning techniques.
· Have a good working knowledge of Low Power Design Techniques.
· Experienced in pad choice, placement, package constraints and applying trade-offs for optimal solutions.
· Can recommend and write strategies for clock tree synthesis and timing convergence and verification.
· Have a good working knowledge of Signal Integrity.
· Understand design-for-test implementation and the consequences on the architecture.
· Have a good working knowledge of off-chip interfaces.
· Be familiar with all currently available design techniques with a view of the benefits and trade-offs.
· Have a working knowledge of related domains, e.g. analogue, test and IC Design.
· Network and maintain contact with other semiconductor physical design groups, including The Technology & Customer Engineering group (TCG) and Innovation Centres.
· Is able to provide guidance on e.g. design for Low cost, High performance and fast TtM.
· Is aware of technology offerings and their benefits/limitations, e.g. processes, libraries, design flows and how they interlink.
· Have experience of direct customer contact.
· Be a good team worker.
· Have good communication and presentation skills.

Agency/Employer: The Eurolink PL
Town or City: Southampton
Location: Hampshire
Sector: Electronics
Related Job Titles: Physical Design Engineer
Permanent/Contract:
Experience: 0 years
Date: 29-07-2004
Salary: Not specified

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