VLSI Design Engineer

Name: jacob jacob
Description:

I would like to work in your esteemed organization in VLSI (ASIC/FPGA/ VHDL/Verilog) field.Now I am doing my Main Project in over Institution, the tite "Impementing ETHERNET MEDIA ACCESS CONTROLLER in VHDL using FPGA Advantage" the tarnsmitting side

Experience: 0 years
Looking for jobs in North East, United Kingdom, London
Presently living in Kerala, india
Area: Abroad
Sector: Other
Age: 29 years
Job title: VLSI Design Engineer
Date last update: 29 January 2006

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